can u help me in reversible alu using logic gates
Im sure we can. Post what you have so far and post what errors you've got ajnd we'll help
module fsm_fa(data,su1,rst,clk,sum1,e1);
input clk,rst;
input [1:0]su1;
input [2:0]data;
output reg [1:0]sum1;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5,s6=3'd6,s7=3'd7;
reg [2:0]ps,ns;
output reg e1;
reg sum,carry;
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
ps<=s0;
else
ps<=ns;
end
always@(ps,data)
begin
case(data)
s0: begin
sum<=0;
carry<=0;
ns<=s1;
end
s1: begin
sum<=1;
carry<=0;
ns<=s2;
end
s2: begin
sum<=1;
carry<=0;
ns<=s3;
end
s3: begin
sum<=0;
carry<=1;
ns<=s4;
end
s4: begin
sum<=1;
carry<=0;
ns<=s5;
end
s5: begin
sum<=0;
carry<=1;
ns<=s6;
end
s6: begin
sum<=0;
carry<=1;
ns<=s7;
end
s7: begin
sum<=1;
carry<=1;
ns<=s0;
end
endcase
sum1<={sum,carry};
end
always@(sum1,su1)
begin
if(sum1==su1)
e1=0;
else
e1=1;
end
endmodule